1. Field of the Invention
The present invention pertains generally to computer systems and more particularly to systems and methods of controlling register access in an electronic circuit.
2. Background of the Invention
A computer system typically includes a host data bus that conveys data among resources within the system. For example, it is popular for modern personal computer systems to have a host bus that complies with the Peripheral Component Interconnect (PCI) specification. The PCI host bus may support a variety of peripherals, including graphics cards, SCSI adapters and sound adapters.
In some applications, a host PCI bus may also support a host controller interface (HCI) to a second bus, such as a bus complying with the IEEE 1394-1995 Standard for a High-performance Serial Bus, Aug. 30, 1996 (the "1394 Standard"), incorporated herein by reference. In the case of an HCI supporting an IEEE 1394 bus, it is preferable that the controller comply with the 1394 Open Host Controller Interface Specification, Release 1.0, Oct. 20, 1997, herein incorporated by reference, which defines requirements of a standard 1394 Open HCI. For example, a 1394 bus may connect peripherals to a host computer system.
The 1394 Standard defines the standard characteristics of a 1394 bus and devices attached thereto. For example, a 1394-compliant device on a 1394-compliant bus must communicate with an HCI following a specific protocol, defined in the 1394 Standard. One aspect of this communication protocol is a set of lock transactions, including, for example: mask.sub.-- swap, compare.sub.-- swap, fetch.sub.-- add, little.sub.-- add, bounded.sub.-- add, and wrap.sub.-- add. Generally, a lock transaction is a transaction accessing a resource that requires more than one clock cycle to complete and prevents access to the same resource by another transaction until it completes.
According to the 1394 Standard, the compare.sub.-- swap function (the "compare-and-swap" function) is required to access a sequence of bus management registers: the BUS.sub.-- MANAGEMENT.sub.-- ID register, the BANDWIDTH.sub.-- AVAILABLE register, the CHANNELS.sub.-- AVAILABLE.sub.-- HI register, and the CHANNELS.sub.-- AVAILABLE.sub.-- LO register. The 1394 standard specifies that lock transactions may be implemented in hardware or software. A hardware implementation of a compare-and-swap function requires more than one clock cycle to execute completely.
FIG. 1 depicts a prior implementation of a 1394 host controller 100 that does not comply with the 1394 Open HCI specification, which requires a hardware implementation of the lock transaction circuitry. Bus management registers 116 are implemented in the host memory of host system 101. The 1394 link and physical layer 102 is connected to 1394 bus 104, and host bus interface 106 is connected to host bus 108. The 1394 link and physical layer 102 communicates with host bus interface 106 via the physical response unit 110, physical read request unit 112, and physical write request unit 114 to access registers in a physical address range. Write lock requests, such as compare-and-swap operations, to bus management registers 116 from nodes located on the 1394 bus 104 are received by the 1394 link and physical layer 102 in the form of packet data and sent to host-resident software for execution. The host software coordinates overlapping compare-and-swap operations from competing buses by scheduling such requests sequentially on a first come, first served basis. In other words, the software acts as a gateway to guarantee the sequential, non-overlapping execution of overlapping compare-and-swap requests.
The 1394 Open HCI specification defines characteristics of a standard 1394 host controller. Among other requirements, the 1394 Open HCI requires a hardware implementation for performing lock transactions from one or more buses, including specified data, argument and control registers associated with each supported bus. In a configuration with more than one bus, nodes from multiple buses may attempt to access a shared target register simultaneously. In other words, each bus can independently initiate a lock transaction using its respective data, compare, and control register set. Because a compare-and-swap function requires more than one clock cycle to complete, there is substantial opportunity for one bus to start a compare-and-swap operation while the other bus is performing this same operation on the same register (i.e., overlapping execution of compare-and-swap operations). If allowed, such an occurrence may cause the data in the target register to become corrupted. This possibility of corrupted data exists for any host controller interface that supports potentially simultaneous lock transactions from two or more buses to the same target register. In 1394 Open HCI systems with multiple 1394 buses, each 1394 bus is associated with its own hardware implementation of bus management registers and lock transaction circuitry.
The 1394 Open HCI specification does not, however, define the actual hardware implementation of the circuitry for such lock transactions. That is, the 1394 Open HCI specifies that a compliant HCI satisfy certain functional requirements, but the electrical circuit that implements those functional requirements is undefined. Therefore, need exists for a circuit and method to coordinate competing lock transactions directed to the same target register so as to prevent a collision that could cause data corruption.